
module ysyx_20220337_IFU (
    input         clk,
    input         rst,
    input         branch,
    input  [63:0] dnpc,
    
    output reg [63:0] pc_addr
);
    wire [63:0]snpc ;
    wire [63:0]npc  ;
    assign snpc = pc_addr + 64'h4;
    assign npc  = branch?  dnpc : snpc;
    always@(posedge clk)begin
        if(rst == 1'b1)begin
            pc_addr <= 64'h0000_0000_8000_0000;
        end
        else begin
            pc_addr <= npc;
        end
    end
endmodule
